The present invention relates generally to semiconductor devices, and more particularly to the manufacturing processes of flip chip ball grid arrays (FCBGAs) using semiconductor substrate having a crystal orientation of (100).
Consumer electronic products such as cell phones, PDAs, digital cameras, etc. are getting smaller, faster, and smarter. Consequently, electronics packaging and assembly capabilities must keep pace. Improvements in materials, equipment performance, and process controls are allowing more companies to move beyond standard surface mount technology (SMT) and into the world of advanced assembly technology. This evolution of large scale integration (LSI) technology is driving package technology growth towards smaller physical size, higher pin count, and higher performance packages. FCBGAs (Flip Chip Ball Grid Arrays) provide an excellent solution to these requirements. An FCBGA is a SMT (surface mount) package which utilizes both flip chip and ball grid array technology. The flip chip technology attaches the semiconductor die to the package substrate internal to the package, while the ball grid array technology attaches the completed package to the printed circuit board. The package substrate is typically comprised of a BT, FR4, FR5, polymer film, PCB, ceramic, glass, or metal lead frame.
The flip chip technology utilizes the flip chip microelectronic assembly, which is the direct electrical connection of face down (hence “flipped” when compared to the conventional wire bond technology layout) electrical components onto substrates, circuit boards, or carriers, by means of conductive solder bumps installed on the flip chip bond pad. The conductive bumps provide the electrical connection to the substrate (in lieu of wire bonds), and also provide a physical standoff between the chip and the substrate. The extensive use of flip chip packaging has been due to its advantages of: decreased size, increased performance, flexibility, reliability, and reduced fabrication cost over other packaging methods. Eliminating packages and bond wires reduce the required board area by up to 95 percent. Flip chip technology offers the highest speed electrical performance of any assembly method. Elimination of the bond wires reduces the effects of inductance and capacitance of the connection by a factor of ten. The result is high speed off-chip interconnections.
In addition, flip chips give the greatest input/output connection flexibility. Conventional wire bond connections are limited to the perimeter of the die. Therefore, as the interconnections increase, the die size may also have to increase to allow for the additional interconnects. However, flip chips can utilize the whole area under the die, accommodating many more connections on a smaller die. The flip chip technology is mechanically the most rugged of all interconnection methods. An adhesive underfill between the die and the package substrate form a solid block of cured epoxy. The flip chip interconnect method is typically the lowest cost interconnection method for high volume automated production. There are three stages in flip chip assemblies: bumping the die, attaching the bumped die to the substrate, and filling the space under/around the die (underfill) to the substrate with an electrically non-conductive material.
The ball grid array (BGA) technology is a conventional SMT connection scheme used to attach the semiconductor device package to a printed circuit board through the use of solder balls on the bottom of the semiconductor device package. The semiconductor device package external connections are arranged as an array of conducting pads on the base of the package. The conducting pads have small solder balls attached to provide the connection to a printed circuit board. There are many advantages to this type of SMT package, such as: lower cost, higher density I/O, less board area utilization, and improved electrical, mechanical, and thermal characteristics.
These processing techniques typically require a thorough consideration of silicon crystal orientation. Certain device properties can depend upon the orientation of the crystal lattice structure. Each crystal orientation has different chemical, mechanical, and electrical properties, such as oxidation, rate, interface density, bonding strength, bonding temperature, capacitances and currents. Therefore, certain processing techniques must consider the orientation of the crystal lattice structure.
The integrated circuit die substrate typically used in conventional FCBGA packages is a silicon crystal wafer that is cut on the (110) plane orientation. There are multiple orientation planes in the silicon crystal that can be used. The planes are defined by the “Miller Indices” methodology, which provides a conventional method to specify planes and direction in a silicon crystal. Common orientations classified by the “Miller indices” are (100), (011), (110), and (111). The orientation of the wafer is classified by which orientation plane the surface of the wafer is parallel to. The surface might not be exactly parallel, but slightly different, and the difference is called the displacement angle or the off angle orientation. The relationship between the crystal's orientation and the radius is marked by either a notch or a flat cut into the wafer, and the orientation adherent to the technology must be considered in modern-day semiconductor processing.
Desirable in the art of FCBGA semiconductor device manufacturing are improved device packaging designs that provide increased electrical, mechanical, and thermal performance at lower cost.